Design of Low-Power DPA-Resistant Cryptographic Functional Units
نویسندگان
چکیده
A design methodology is proposed to implement instructionset extensions for cryptographic processors and hardware accelerators with the aim to improve their potential robustness against Differential Power Analysis (DPA) attacks. The approach has a high-level component that is based on identifying the critical units and functions in a design with respect to DPA resistance, and a gate-level component that is based on implementing the critical units using an inherently DPA-resistant circuit design style. Our methodology can be used to automatically identify and to isolate the DPAcritical nodes, as well as to map them onto a robust cell library that is compatible with conventional deep-submicron CMOS technologies.
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